Conventionally, there exist semiconductor devices which are produced by soldering a semiconductor chip such as an LSI chip on a wiring board having an Au layer formed on a surface thereof and sealing the chip and the board with a resin. The Au layer on the surface of the wiring board is formed by plating or sputtering in order to ensure solder wettability and prevent oxidation of interconnections. When the semiconductor chip is soldered on such a wiring board, however, an Au—Sn alloy layer is formed from Au of the Au layer and Sn of a solder in an interface between the Au layer and the solder, thereby reducing the bonding strength between the semiconductor chip and the wiring board. This causes a problem that cracking occurs from the Au—Sn alloy layer due to heat shock, heat cycle and the like.
To solve this problem, it is proposed to prevent the formation of the Au—Sn alloy layer by significantly reducing the thickness of the Au layer (see, for example, Patent Document 1). However, the formation of the Au—Sn alloy layer is not perfectly prevented by the reduction of the thickness of the Au layer, as long as contacts exist between the Au layer and the solder. Therefore, the Au—Sn alloy layer is locally formed, so that the reduction in the bonding strength between the semiconductor chip and the wiring board is not satisfactorily prevented. Further, the reduction of the thickness of the Au layer reduces the solder wettability. This results in occurrence of voids and improper self-alignment of the semiconductor chip in the soldering of the semiconductor chip.
Therefore, it is proposed to improve the bonding strength between the semiconductor chip and the wiring board by an anchoring effect by forming undulations in an interface between the Au—Sn alloy layer and the solder layer (see, for example, Patent Document 2). With the arrangement according to this proposal, the Au layer has a sufficient thickness, thereby preventing the occurrence of the voids and the improper self-alignment of the semiconductor chip in the soldering of the semiconductor chip.    Patent Document 1: Japanese Unexamined Patent Publication No. 06-283844 (1994)    Patent Document 2: Japanese Unexamined Patent Publication No. 2004-22608